The present invention relates generally to integrated circuits, and more particularly, to an analog-to-digital converter that is gated to avoid power supply noise.
System-on-chips (SoCs) include various digital as well as analog components that are integrated on a single chip. Analog-to-digital converters (ADC) are highly sensitive to noise. Unfortunately, certain components of the SoC, such as switched-mode power supplies (SMPS) and peripheral interfaces, generate noise so if they are located near the ADC, the noise crosses over to the ADC and degrades its performance. The SMPS is one of the major sources of noise in the SoC. The SMPS converts an unregulated supply voltage to a regulated supply voltage, and includes a high frequency switch (usually a metal-oxide semiconductor (MOS) transistor or a bipolar junction transistor (BJT)), referred to as a pass element. The pass element switches between on and off states during voltage regulation, which results in the generation of noise. When the SMPS is located near the ADC, the noise couples to the ADC, which degrades the ADC performance.
Various solutions are available to overcome the above-mentioned problem. One solution is to use a capacitor-input filter at the output of the SMPS to reduce noise. However, as the switching frequency of the pass element increases, the capacitive reactance of the capacitor decreases, which impairs ability of the capacitor-input filter to reduce the noise of the SMPS. Another solution is to use choke filters that include an inductor connected in series and a capacitor connected in parallel with the output of the SMPS. However, the inductor introduces magnetic field interferences on the ADC, which again degrades performance and also increases cost. Using passive components such as capacitors and inductors further increases chip area, which restricts their use in small-scale circuits.
Yet another solution uses a software application to manage the noise coupled to the ADC. A processor runs a scheduling algorithm that schedules ADC tasks based on the switching activity of the SMPS pass element, i.e., the ADC functions only when the pass element is not switching. However, this solution fails to reduce the noise coupling for SoCs that do not include a processor. The ADC throughput also suffers because software-based ADC scheduling consumes time. Scheduling algorithms further negatively affect the sampling rate of the ADC.
Therefore it would be advantageous to have an ADC that is not susceptible to on-chip noise and maintains a uniform sampling rate, yet does not consume too much area and power.